LPC: An Error Correction Code for Mitigating Faults in 3D Memories

The radiation sensitivity of memory cells increases dramatically as CMOS manufacture technology scales down; therefore, the reliability memories has become a challenge. 3D gained attention for having several advantages compared to 2D counterpart, such high integration density, performance, low power, and communication speed. Although studies are targeting memories, effects on using this have received little attention. This work introduces Line Product Code (LPC), modified product code-based Error Correction (ECC) that uses both Hamming parity in rows columns implement reliable memories. We implemented two lightweight LPC-based decoding algorithms interleaved (LPCa-I) non-interleaved (LPCa) versions, which allowed us analyze LPC through set simulation cases considers four severity levels error incidence. experimental results showed effectiveness algorithms, reaching correction rates up 2.3 times higher other Hamming-based algorithms.